library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clock is
  port(clk0:in std_logic;--时钟输入信号
       clr:in std_logic;--电子钟清零使能信号
       settime:in std_logic;-- 电子钟重置使能信号
       choice:in std_logic_vector(2 downto 0);-- 电子钟重置位选择
       add:in std_logic;-- 单次脉冲（控制重置的时间设置）
       fqout:out std_logic_vector(26 downto 0);   --显示输出
       ring:out std_logic);--整点报时：响铃输出
end;

architecture art of clock is
     
component divider
    port (clk:in std_logic;
          clk1Hz: out std_logic );
end component;

component counter
    port(clk1:in std_logic;
         clr:in std_logic;
         settime:in std_logic;
         qin1:in std_logic_vector(23 downto 0);
         qout:out std_logic_vector(23 downto 0));
end component;

component set
   port(choice:in std_logic_vector(2 downto 0);
        add:in std_logic;
         qout1:out std_logic_vector(23 downto 0));
end component;

component screen 
   port(qin:in std_logic_vector(23 downto 0);
        fqout:out std_logic_vector(26 downto 0);
        ring:out std_logic);
end component;

--信号定义
signal clk01:std_logic;
signal sout1:std_logic_vector(23 downto 0);
signal sout:std_logic_vector(23 downto 0);

begin
u1:divider port map(clk=>clk0,clk1Hz=>clk01);
u2:counter port map(settime=>settime,qout=>sout,clr=>clr,clk1=>clk01,qin1=>sout1);
u3:set port map(choice=>choice,add=>add,qout1=>sout1);
u4:screen port map(qin=>sout,fqout=>fqout,ring=>ring);

end art;
